The present invention evolved from efforts to provide improved sampling circuitry for post-correlator signal processing in a direct sequence spread spectrum (DSSS) radio system, though the invention is of course not limited thereto.
In a DSSS radio system, a data bit is spread out into a plurality of chips, and is transmitted as a burst of many chips which modulate an RF carrier. For example, a data bit in a signal stream having a rate of 100 kilobits per second may be transmitted as a group of 1,000 chips or mini-bits in a signal stream having a rate of 100 megabits per second. The receiver has a correlator which functions as a matched filter to output very short duration analog voltage spikes (correlation peaks) when the group of chips matches a given chip code to thus indicate that a data bit 1 or a data bit 0 has been received. A classical result of matched filter theory is that the signal-to-noise ratio (SNR) is maximized at one instant in time. The SNR is at a maximum at the time that a correlation peak occurs.
The receiver correlator may be implemented before or after demodulation but is most easily understood in its baseband (after demodulation) form. The baseband correlator usually includes a comparator delay line and a summing amplifier. The comparator delay line receives the group of chips serially therethrough, one chip at a time. In the above example, this comparator delay line would have 1,000 serial chip locations, and the group of 1,000 chips would be serially shifted through the comparator delay line at the 100 megabit per second rate. Each location has a tap for comparing whether the chip currently in that location matches a predetermined chip code value for that location. Each of the location taps is connected in parallel to a summing amplifier.
The output of the summing amplifier is maximum when each of the 1,000 taps thereinto are high, which indicates that each of the 1,000 chips in the comparator delay line matches the predetermined chip code value for each of the 1,000 locations. The summing amplifier then outputs a correlation peak or voltage spike to indicate a digital 1 data bit, i.e., the 1,000 chips at the 100 megabit per second rate represents a single data bit having a value 1 at the 100 kilobit per second data rate. Another summing amplifier and a different chip code is provided for indicating a data bit value of 0. Transmission channel effects such as waveform distortion, noise, and interference will act to reduce the ideal amplitude of the correlation peak.
Since the group of 1,000 chips is shifted through the comparator delay line at a 100 megabit per second rate, a correlation peak has a very short duration, namely about 10 nanoseconds. This correlation peak duration of course depends on the amount of spreading of the original data bit, which is in turn constrained by the speed of the correlator hardware, particularly the comparator delay line and the summing amplifier. For example, if a 100 kilobit per second data stream bit is spread to only 4 chips, then the comparator delay line need only be 4 chips long, with the 4 chips being shifted therethrough at a rate of 400 kilobits per second. In this example, the output pulses of the summing amplifier may have a duration of 2.5 microseconds.
The higher the initial data rate, or the greater the amount of spreading, the shorter the duration of the output voltage spikes from the summing amplifier in the receiver correlator. These correlator output pulses are of varying height, depending on the percentage of chip location matches in the comparator delay line. Peaks occur at variable times and this, coupled with their short duration, presents difficulties in detection. Extremely fast signal processing hardware is usually needed following the receiver correlator in order to extract information from the short duration correlation peaks. The present invention involves this post-correlator signal processing, and enables the use of much slower signal processing hardware than would otherwise be required.
Recent innovations in surface acoustic wave devices allow correlators to be easily implemented at an intermediate frequency (IF) before demodulation. Consequently, this is a very common implementation. In this case the correlation peak shape is generally not rectangular, but rather is approximately triangular in shape.
A standard post-correlator sampler composed of a sample and hold circuit performs a sampling operation on the correlator output at given sampling times. If a correlation peak occurs at sometime other than a sampling time, then there is no signal generated at the sampler output for that spike, and hence that spike is missed. In order to avoid missing any correlation peak spikes, the sampling interval must be made very small, i.e., many closely spaced samples must be taken. For a baseband correlator (or a rectangular correlation peak), the sampling times can be spaced by no more than the duration of the correlation peak. For other correlators (not baseband) the correlation peak is a changing analog value during its duration, and the height of the peak represents vital information. As above noted, this latter non-baseband correlator (before demodulation) is a very common type.
In order to extract information regarding the height of the peak, the sampling interval for the standard post-correlator sampler must be further reduced such that a plurality of sampling times occur within the duration of a single correlation peak. For example, to take four samples during a 10 nanosecond correlation peak duration would require a sampling interval of only 2.5 nanoseconds between sampling times.
A one-shot generator is a commonly known digital logic element which produces an adjustable width output pulse when triggered by a short duration input pulse. The one-shot operates as a pulse stretcher, since short input pulses produce longer output pulses. The one-shot could then be followed by lower speed digital logic for further signal processing requirements. This approach is objectionable because the one-shot lacks a transfer of analog information pertaining to the amplitude of the peaks from the correlator. The one-shot is a strictly digital device with a fixed trigger level threshold. Because of the loss of analog information, finer time resolution in the post-correlator signal processing is required to obtain equivalent performance to a system which retains this analog information.
The digital approach could be modified to allow analog information from the correlator to be retained by using several one-shots, each with a different trigger threshold. By observing which one-shots are triggered, at any given time the amplitude of the correlator output signal could be deduced. This could be accomplished with digital logic and any further signal processing could also be digital in nature. This digital processing would require faster and/or more hardware.
Thus, while digital pulse stretching and its attendant digital circuitry may be utilized for post-correlator signal processing to permit further signal processing thereafter to be accomplished with slower speed hardware, this type of digital intermediate sampler itself may require very fast and/or complex hardware which must be traded off against the speed and complexity reduction in the hardware thereafter. That is, while the sampler does enable slower responding hardware to be used thereafter, some of the savings are offset or negated by the additional speed requirements and/or complexity in the sampler itself.
There is thus a need for a post-correlator sampler which enables slower speed processing hardware thereafter and which is itself simple and efficient.